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C161PI
www.infineon.com
Microcontrollers
C166 Family
16-Bit Single-Chip Microcontroller C161PI
Data Sheet 1999-07
Preliminary
C161PI Revision History: Previous Versions:
1999-07 Preliminary 1998-05 1998-01 1997-12 (C161RI / Preliminary) (C161RI / Advance Information) (C161RI / Advance Information)
Page --4, 5, 7 14 15 23 24 25, 51, 52 36, 37 39, 44 45 - 50 54 ff.
Subjects 3 V specification introduced Signal FOUT added XRAM description added Unlatched CS description added Block Diagram corrected Description of divider chain improved ADC description updated to 10-bit Revised description of Absolute Max. Ratings and Operating Conditions Power supply values improved Revised description for clock generation including PLL Standard 25-MHz timing
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com The C161PI is the successor of the C161RI. Therefore this data sheet also replaces the C161RI data sheet (see also revision history).
Edition 1999-07 Published by Infineon Technologies AG i. Gr., St.-Martin-Strasse 53 D-81541 Munchen (c) Infineon Technologies AG 1999. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
C166 Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary C161PI 16-Bit Microcontroller
C161PI
* High Performance 16-bit CPU with 4-Stage Pipeline - 80 ns Instruction Cycle Time at 25 MHz CPU Clock - 400 ns Multiplication (16 x 16 bit), 800 ns Division (32 / 16 bit) - Enhanced Boolean Bit Manipulation Facilities - Additional Instructions to Support HLL and Operating Systems - Register-Based Design with Multiple Variable Register Banks - Single-Cycle Context Switching Support - 16 MBytes Total Linear Address Space for Code and Data - 1024 Bytes On-Chip Special Function Register Area * 16-Priority-Level Interrupt System with 27 Sources, Sample-Rate down to 40 ns * 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) * Clk. Generation via on-chip PLL (1:1.5/2/2.5/3/4/5), via prescaler or via direct clk. inp. * On-Chip Memory Modules - 1 KByte On-Chip Internal RAM (IRAM) - 2 KBytes On-Chip Extension RAM (XRAM) * On-Chip Peripheral Modules - 4-Channel 10-bit A/D Converter with Programm. Conversion Time down to 7.8 s - Two Multi-Functional General Purpose Timer Units with 5 Timers - Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) - I2C Bus Interface (10-bit Addressing, 400 KHz) with 2 Channels (multiplexed) * Up to 8 MBytes External Address Space for Code and Data - Programmable External Bus Characteristics for Different Address Ranges - Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width - Five Programmable Chip-Select Signals * Idle and Power Down Modes with Flexible Power Management * Programmable Watchdog Timer and Oscillator Watchdog * On-Chip Real Time Clock * Up to 76 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis * Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards * On-Chip Bootstrap Loader * 100-Pin MQFP / TQFP Package
Data Sheet
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This document describes the SAB-C161PI-LM, the SAB-C161PI-LF, the SAF-C161PILM and the SAF-C161PI-LF. For simplicity all versions are referred to by the term C161PI throughout this document.
Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: * * * * the derivative itself, i.e. its function set the specified temperature range the package the type of delivery.
For the available ordering codes for the C161PI please refer to the Product Catalog Microcontrollers", which summarizes all available microcontroller variants.
Note: The ordering codes for Mask-ROM versions are defined for each product after verification of the respective ROM code.
Data Sheet 2 1999-07
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Introduction The C161PI is a derivative of the Infineon C166 Family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. The C161PI derivative is especially suited for cost sensitive applications.
VDD VSS
VAREF VAGND
XTAL1 XTAL2 RSTIN RSTOUT NMI EA ALE RD WR/WRL Port 5 6 bit
PORT0 16 bit PORT1 16 bit Port 2 8 bit
C161PI
Port 3 15 bit Port 4 7 bit Port 6 8 bit
Figure 1
Logic Symbol
Data Sheet
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Pin Configuration MQFP Package (top view)
Figure 2
Data Sheet
P4.5/A21 P4.6/A22 RD WR/WRL READY ALE EA VSS VDD P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 VSS VDD P0H.0/AD8
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P5.2/AN2 P5.3/AN3 P5.14/T4EUD P5.15/T2EUD VSS XTAL1 XTAL2 VDD P3.0/SCL0 P3.1/SDA0 P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13/SCLK P3.15/CLKOUT/ FOUT VSS VDD P4.0/A16 P4.1/A17 P4.2/A18 P4.3/A19 P4.4/A20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P5.1/AN1 P5.0/AN0 VAGND VAREF P2.15/EX7IN P2.14/EX6IN P2.13/EX5IN P2.12/EX4IN P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/SDA2 P6.6/SCL1 P6.5/SDA1 P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0
C161PI
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NMI RSTOUT RSTIN VDD VSS P1H.7/A15 P1H.6/A14 P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 VDD VSS P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 P0H.1/AD9
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Pin Configuration TQFP Package (top view)
P5.14/T4EUD P5.15/T2EUD VSS XTAL1 XTAL2 VDD P3.0/SCL0 P3.1/SDA0 P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13/SCLK P3.15/CLKOUT/ FOUT VSS VDD P4.0/A16 P4.1/A17
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P5.3/AN3 P5.2/AN2 P5.1/AN1 P5.0/AN0 VAGND VAREF P2.15/EX7IN P2.14/EX6IN P2.13/EX5IN P2.12/EX4IN P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/SDA2 P6.6/SCL1 P6.5/SDA1 P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0 NMI RSTOUT RSTIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
C161PI
VDD VSS P1H.7/A15 P1H.6/A14 P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 VDD VSS P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11
Figure 3
Data Sheet
P4.2/A18 P4.3/A19 P4.4/A20 P4.5/A21 P4.6/A22 RD WR/WRL READY ALE EA VSS VDD P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 VSS VDD P0H.0/AD8 P0H.1/AD9 P0H.2/AD10
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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Table 1
Pin Definitions and Functions
Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP P5 I Port 5 is a 6-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as (up to 4) analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Input T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Input XTAL1: Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.
P5.0 P5.1 P5.2 P5.3 P5.14 P5.15 XTAL1 XTAL2
97 98 99 100 1 2 4 5
99 100 1 2 3 4 6 7
I I I I I I I O
Data Sheet
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Table 1
Pin Definitions and Functions (continued)
Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP P3 IO Port 3 is a 15-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: SCL0 I2C Bus Clock Line 0 SDA0 I2C Bus Data Line 0 CAPIN GPT2 Register CAPREL Capture Input T3OUT GPT1 Timer T3 Toggle Latch Output T3EUD GPT1 Timer T3 External Up/Down Ctrl.Inp T4IN GPT1 Timer T4 Count/Gate/Reload/ Capture Input T3IN GPT1 Timer T3 Count/Gate Input T2IN GPT1 Timer T2 Count/Gate/Reload/ Capture Input MRST SSC Master-Rec. / Slave-Trans. Inp/Outp. MTSR SSC Master-Trans. / Slave-Rec. Outp/Inp. TxD0 ASC0 Clock/Data Output (Async./Sync.) RxD0 ASC0 Data Input (Async.) or I/O (Sync.) External Memory High Byte Enable Signal, BHE External Memory High Byte Write Strobe WRH SCLK SSC Master Clock Outp. / Slave Clock Inp. CLKOUT System Clock Output (=CPU Clock) FOUT Programmable Frequency Output
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.15
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
I/O I/O I O I I I I I/O I/O O I/O O O I/O O O
Note: Pins P3.0 and P3.1 are open drain outputs only.
Data Sheet
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Table 1
Pin Definitions and Functions (continued)
Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP P4 IO Port 4 is a 7-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 4 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 4 is selectable (TTL or special). Port 4 can be used to output the segment address lines: A16 Least Significant Segment Address Line A17 Segment Address Line A18 Segment Address Line A19 Segment Address Line A20 Segment Address Line A21 Segment Address Line A22 Most Significant Segment Address Line External Memory Read Strobe. RD is activated for every external instruction or data read access. External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRLmode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. An internal pullup device will hold this pin high when nothing is driving it. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes.
P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 RD WR/ WRL
24 25 26 27 28 29 30 31 32
26 27 28 29 30 31 32 33 34
O O O O O O O O O
READY 33
35
I
ALE
34
36
O
Data Sheet
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Table 1
Pin Definitions and Functions (continued)
Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP EA 35 37 I External Access Enable pin. A low level at this pin during and after Reset forces the C161PI to begin instruction execution out of external memory. A high level forces execution out of the internal program memory. "ROMless" versions must have this pin tied to `0'. PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of external bus configurations, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: D0 - D7 D0 - D7 P0H.0 - P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15 PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.
PORT0 P0L.0-7 3845 P0H.0-7 4855
IO 4047 5057
PORT1 P1L.0-7 5663 P1H.0-7 6673
IO 5865 6875
Data Sheet
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Table 1
Pin Definitions and Functions (continued)
Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP RSTIN 76 78 I/O Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the C161PI. An internal pullup resistor permits power-on reset using only a capacitor connected to 9SS. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN line is internally pulled low for the duration of the internal reset sequence upon any reset (HW, SW, WDT). See note below this table.
Note: To let the reset configuration of PORT0 settle and to let the PLL lock a reset duration of ca. 1 ms is recommended.
RST OUT 77 79 O Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C161PI to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally.
NMI
78
80
I
Data Sheet
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Table 1
Pin Definitions and Functions (continued)
Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP P6 IO Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The Port 6 pins also serve for alternate functions: Chip Select 0 Output CS0 Chip Select 1 Output CS1 Chip Select 2 Output CS2 Chip Select 3 Output CS3 Chip Select 4 Output CS4 SDA1 I2C Bus Data Line 1 SCL1 I2C Bus Clock Line 1 SDA2 I2C Bus Data Line 2
P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 P2
79 80 81 82 83 84 85 86
81 82 83 84 85 86 87 88
O O O O O I/O I/O I/O IO
Note: Pins P6.7-5 are open drain outputs only.
Port 2 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The Port 2 pins also serve for alternate functions: EX0IN Fast External Interrupt 0 Input EX1IN Fast External Interrupt 1 Input EX2IN Fast External Interrupt 2 Input EX3IN Fast External Interrupt 3 Input EX4IN Fast External Interrupt 4 Input EX5IN Fast External Interrupt 5 Input EX6IN Fast External Interrupt 6 Input EX7IN Fast External Interrupt 7 Input Reference voltage for the A/D converter. Reference ground for the A/D converter.
P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15
87 88 89 90 91 92 93 94 95 96
89 90 91 92 93 94 95 96 97 98
I I I I I I I I -
9AREF 9AGND
Data Sheet
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Table 1
Pin Definitions and Functions (continued)
Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP
9DD
6, 23, 37, 47, 65, 75 3, 22, 36, 46, 64, 74
8, 25, 39, 49, 67, 77 5, 24, 38, 48, 66, 76
Digital Supply Voltage: + 5 V or + 3 V during normal operation and idle mode. 2.5 V during power down mode Digital Ground.
9SS
Note: The following behaviour differences must be observed when the bidirectional reset is active:
* Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset. * The reset indication flags always indicate a long hardware reset. * The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader may be activated when P0L.4 is low. * Pin RSTIN may only be connected to external reset devices with an open drain output driver. * A short hardware reset is extended to the duration of the internal reset sequence.
Data Sheet
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Functional Description The architecture of the C161PI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C161PI.
Note: All time specifications refer to a CPU clock of 25 MHz (see definition in the AC Characteristics section).
(no internal ROM)
32
Instr./Data 16
Data 16 Data
Dual Port
&&RUH
&38 &RUH &38
16
Internal RAM
AF7r
XTAL
OSC Oscillator (input: 16MHz; (16MHz) prescaler PLL or direct drive) External Instr./Data
XBUS (16-bit NON MUX Data / Addresses)
3(&
Watchdog 11 ext. IR 16
16
Interrupt Controller
Peripheral Data
IC-Bus Interface XRAM 2 KByte
Interrupt Bus
8 Port 6
16 Port 0
External Bus (MUX only) & XBUS Control, CS Logic (4 CS)
4Channel 10-bit 8-bit ADC
USART
Sync. Channel (SPI) SSC BRG
GPT 1 T2 T3 T4
GPT 2 T5 T6
RTC
ASC BRG
7 Port 4 Port 1 16 Port 5 6 Port 3 15 Port 2
C161RI V0.1
8
Figure 4
Block Diagram
Data Sheet
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Memory Organization The memory space of the C161PI is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. 1 KByte of on-chip Internal RAM (IRAM) is provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 Family. 2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks, or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with maximum speed. In order to meet the needs of designs where more memory is required than is provided on chip, up to 8 MBytes of external RAM and/or ROM can be connected to the microcontroller.
Data Sheet
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External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: - - - - 16-/18-/20-/23-bit Addresses, 16-bit Data, Demultiplexed 16-/18-/20-/23-bit Addresses, 16-bit Data, Multiplexed 16-/18-/20-/23-bit Addresses, 8-bit Data, Multiplexed 16-/18-/20-/23-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/ output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which allow to access different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue logic. The C161PI offers the possibility to switch the CS outputs to an unlatched mode. In this mode the internal filter logic is switched off and the CS signals are directly generated from the address. The unlatched CS mode is enabled by setting CSCFG (SYSCON.6). Access to very slow memories is supported via a particular `Ready' function. For applications which require less than 8 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines at all. It outputs all 7 address lines, if an address space of 8 MBytes is used.
Data Sheet
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Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C161PI's instructions can be executed in just one machine cycle which requires 2 CPU clocks (4 TCL). For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the socalled `Jump Cache', reduces the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 5
CPU Block Diagram
Data Sheet
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The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C161PI instruction set which includes the following instruction classes: - - - - - - - - - - - - Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.
Data Sheet
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Interrupt System With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C161PI is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C161PI supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C161PI has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. The following table shows all of the possible C161PI interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not used by associated peripherals, may be used to generate software controlled interrupt requests by setting the respective interrupt request bit (xIR).
Data Sheet
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Table 2
C161PI Interrupt Nodes Enable Flag CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE T2IE T3IE T4IE T5IE T6IE CRIE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE XP0IE XP1IE XP2IE XP3IE Interrupt Vector CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT T2INT T3INT T4INT T5INT T6INT CRINT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT XP0INT XP1INT XP2INT XP3INT Vector Location 00'0060H 00'0064H 00'0068H 00'006CH 00'0070H 00'0074H 00'0078H 00'007CH 00'0088H 00'008CH 00'0090H 00'0094H 00'0098H 00'009CH 00'00A0H 00'00A4H 00'00A8H 00'011CH 00'00ACH 00'00B0H 00'00B4H 00'00B8H 00'00BCH 00'0100H 00'0104H 00'0108H 00'010CH Trap Number 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 22H 23H 24H 25H 26H 27H 28H 29H 2AH 47H 2BH 2CH 2DH 2EH 2FH 40H 41H 42H 43H
Source of Interrupt or Request PEC Service Request Flag External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error I2C Data Transfer Event I2C Protocol Event X-Peripheral Node 2 PLL Unlock / RTC CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR T2IR T3IR T4IR T5IR T6IR CRIR ADCIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR XP0IR XP1IR XP2IR XP3IR
Data Sheet
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The C161PI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during run-time: Table 3 Hardware Trap Summary Trap Flag Trap Vector RESET RESET RESET NMI STKOF STKUF UNDOPC PRTFLT ILLOPA ILLINA ILLBUS Vector Location 00'0000H 00'0000H 00'0000H Trap Trap Number Prio 00H 00H 00H 02H 04H 06H 0AH 0AH 0AH 0AH 0AH III III III II II II I I I I I Exception Condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps: TRAP Instruction
NMITRAP 00'0008H STOTRAP 00'0010H STUTRAP 00'0018H BTRAP BTRAP BTRAP BTRAP BTRAP 00'0028H 00'0028H 00'0028H 00'0028H 00'0028H
[2CH - 3CH] [0BH - 0FH] Any Any [00'0000H - [00H - 00'01FCH] 7FH] in steps of 4H Current CPU Priority
Data Sheet
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General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 16 TCL. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate eg. position tracking. In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on a port pin (T3OUT) eg. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.
Data Sheet
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T2EUD fCPU T2IN 2n : 1 T2 Mode Control
U/D GPT1 Timer T2 Interrupt Request
Reload Capture Interrupt Request T3 Mode Control Toggle FF GPT1 Timer T3 U/D Other Timers Capture Reload T3OTL T3OUT
fCPU
2n : 1
T3IN
T3EUD
T4IN fCPU T4EUD 2n : 1
T4 Mode Control
GPT1 Timer T4 U/D
Interrupt Request
MCT02141
Figure 6
Block Diagram of GPT1
With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler. The count direction (up/down) for each timer is programmable by software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/ underflow.
Data Sheet
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The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can additionally be used to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3's inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode.
fCPU
2n : 1 T5 Mode Control U/D GPT2 Timer T5 Clear Capture Interrupt Request
T3 MUX CAPIN GPT2 CAPREL
Interrupt Request
CT3
Interrupt Request
GPT2 Timer T6 T6 Mode Control U/D
T6OTL
T6OUT
fCPU
2n :
1
Other Timers
Mcb03999C.vsd
Figure 7
Block Diagram of GPT2
Data Sheet
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Real Time Clock The Real Time Clock (RTC) module of the C161PI consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver (IRTC = IOSC / 32) and is therefore independent from the selected clock generation mode of the C161PI. All timers count up. The RTC module can be used for different purposes: * System clock to determine the current time and date * Cyclic time based interrupt * 48-bit timer for long term measurements
T14REL
Reload
T14
8:1
fRTC
Interrupt Request
RTCL
RTCL
Figure 8
RTC Block Diagram
Note: The registers associated with the RTC are not effected by a reset in order to maintain the correct system time even when intermediate resets are executed.
Data Sheet
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A/D Converter For analog signal measurement, a 10-bit A/D converter with 4 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. Overrun error detection/protection is provided for the conversion result register (ADDAT): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. For applications which require less than 4 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the C161PI supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. After each reset and also during normal operation the ADC automatically performs calibration cycles. This automatic self-calibration constantly adjusts the converter to changing operating conditions (e.g. temperature) and compensates process variations. These calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the A/D converter. In order to decouple analog inputs from digital noise and to avoid input trigger noise those pins used for analog input can be disconnected from the digital IO or input stages under software control. This can be selected for each pin separately via registers P5DIDIS (Port 5 Digital Input Disable).
Data Sheet
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Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 780 KBaud and half-duplex synchronous communication at up to 3.1 MBaud @ 25 MHz CPU clock. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. The SSC supports full-duplex synchronous communication at up to 6.25 Mbaud @ 25 MHz CPU clock. It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 3 separate interrupt vectors are provided. The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data.
Data Sheet
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I2C Module The integrated I2C Bus Module handles the transmission and reception of frames over the two-line I2C bus in accordance with the I2C Bus specification. The on-chip I2C Module can receive and transmit data using 7-bit or 10-bit addressing and it can operate in slave mode, in master mode or in multi-master mode. Several physical interfaces (port pins) can be established under software control. Data can be transferred at speeds up to 400 Kbit/sec. Two interrupt nodes dedicated to the I2C module allow efficient interrupt service and also support operation via PEC transfers.
Note: The port pins associated with the I2C interfaces feature open drain drivers only, as required by the I2C specification.
Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 20 s and 336 ms can be monitored (@ 25 MHz). The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).
Data Sheet
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Parallel Ports The C161PI provides up to 76 IO lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three IO ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. The other IO ports operate in push/pull mode, except for the IC interface pins which are open drain pins only. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. All port lines that are not used for these alternate functions may be used as general purpose IO lines. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A22/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output CLKOUT (or the programmable frequency output FOUT). Port 5 is used for the analog input channels to the A/D converter or timer control signals. Port 6 provides the optional chip select signals and interface lines for the IC module. The edge characteristics (transition time) of the C161PI's port drivers can be selected via the Port Driver Control Register (PDCR).
Data Sheet
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Instruction Set Summary The table below lists the instructions of the C161PI in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the "C166 Family Instruction Set Manual". This document also provides a detailled description of each instruction. Table 4 Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR
Data Sheet
Instruction Set Summary Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR
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Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2
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Table 4
Instruction Set Summary (continued) Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand. with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack und update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 2/4 2/4 2/4 4 4 4 4 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2
Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP
Data Sheet
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Special Function Registers Overview The following table lists all SFRs which are implemented in the C161PI in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Registers within on-chip X-Peripherals (IC) are marked with the letter "X" in column "Physical Address". An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Table 5 Name ADCIC ADCON ADDAT ADDAT2 ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 ADEIC C161PI Registers, Ordered by Name Physical Address b FF98H b FFA0H FEA0H F0A0H FE18H FE1AH FE1CH FE1EH b FF9AH 8-Bit Description Addr. CCH D0H 50H E 50H 0CH 0DH 0EH 0FH CDH 86H 8AH 8BH 8CH 8DH 25H C4H C5H C6H C7H A/D Converter End of Conversion Interrupt Control Register A/D Converter Control Register A/D Converter Result Register A/D Converter 2 Result Register Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 A/D Converter Overrun Error Interrupt Control Register Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 GPT2 Capture/Reload Register External Interrupt 0 Control Register External Interrupt 1 Control Register External Interrupt 2 Control Register External Interrupt 3 Control Register
31
Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
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BUSCON0 b FF0CH BUSCON1 b FF14H BUSCON2 b FF16H BUSCON3 b FF18H BUSCON4 b FF1AH CAPREL CC8IC CC9IC CC10IC CC11IC
Data Sheet
FE4AH b FF88H b FF8AH b FF8CH b FF8EH
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Table 5 Name CC12IC CC13IC CC14IC CC15IC CP CRIC CSP DP0L DP0H DP1L DP1H DP2 DP3 DP4 DP6 DPP0 DPP1 DPP2 DPP3 EXICON ICADR ICCFG ICCON ICRTB ICST IDCHIP IDMANUF IDMEM
C161PI Registers, Ordered by Name (continued) Physical Address b FF90H b FF92H b FF94H b FF96H FE10H b FF6AH FE08H b F100H b F102H b F104H b F106H b FFC2H b FFC6H b FFCAH b FFCEH FE00H FE02H FE04H FE06H b F1C0H ED06H ED00H ED02H ED08H ED04H F07CH F07EH F07AH 8-Bit Description Addr. C8H C9H CAH CBH 08H B5H 04H E 80H E 81H E 82H E 83H E1H E3H E5H E7H 00H 01H 02H 03H E E0H X --X --X --X --X --E 3EH E 3FH E 3DH External Interrupt 4 Control Register External Interrupt 5 Control Register External Interrupt 6 Control Register External Interrupt 7 Control Register CPU Context Pointer Register GPT2 CAPREL Interrupt Ctrl. Register CPU Code Segment Pointer Register (8 bits, not directly writeable) P0L Direction Control Register P0H Direction Control Register P1L Direction Control Register P1H Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register CPU Data Page Pointer 0 Register (10 bits) CPU Data Page Pointer 1 Reg. (10 bits) CPU Data Page Pointer 2 Reg. (10 bits) CPU Data Page Pointer 3 Reg. (10 bits) External Interrupt Control Register IC Address Register IC Configuration Register IC Control Register IC Receive/Transmit Buffer IC Status Register Identifier Identifier Identifier Reset Value 0000H 0000H 0000H 0000H FC00H 0000H 0000H 00H 00H 00H 00H 0000H 0000H 00H 00H 0000H 0001H 0002H 0003H 0000H 0XXXH XX00H 0000H XXH 0000H 09XXH 1820H 0000H
1999-07
Data Sheet
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Table 5 Name IDPROG ISNC MDC MDH MDL ODP2 ODP3 ODP6 ONES P0L P0H P1L P1H P2 P3 P4 P5 P5DIDIS P6 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PSW PDCR RP0H
Data Sheet
C161PI Registers, Ordered by Name (continued) Physical Address F078H b F1DEH b FF0EH FE0CH FE0EH b F1C2H b F1C6H b F1CEH b FF1EH b FF00H b FF02H b FF04H b FF06H b FFC0H b FFC4H b FFC8H b FFA2H b FFA4H b FFCCH FEC0H FEC2H FEC4H FEC6H FEC8H FECAH FECCH FECEH b FF10H F0AAH b F108H 8-Bit Description Addr. E 3CH E EFH 87H 06H 07H E E1H E E3H E E7H 8FH 80H 81H 82H 83H E0H E2H E4H D1H D2H E6H 60H 61H 62H 63H 64H 65H 66H 67H 88H E 55H E 84H Identifier Interrupt Subnode Control Register CPU Multiply Divide Control Register CPU Multiply Divide Reg. - High Word CPU Multiply Divide Reg. - Low Word Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 6 Open Drain Control Register Constant Value 1's Register (read only) Port 0 Low Reg. (Lower half of PORT0) Port 0 High Reg. (Upper half of PORT0) Port 1 Low Reg. (Lower half of PORT1) Port 1 High Reg. (Upper half of PORT1) Port 2 Register Port 3 Register Port 4 Register (7 bits) Port 5 Register (read only) Port 5 Digital Input Disable Register Port 6 Register (8 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register CPU Program Status Word Pin Driver Control Register System Startup Config. Reg. (Rd. only)
33
Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 00H FFFFH 00H 00H 00H 00H 0000H 0000H 00H XXXXH 0000H 00H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H XXH
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Table 5 Name RTCH RTCL S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC S0TBUF S0TIC SP SSCBR SSCCON SSCEIC SSCRB SSCRIC SSCTB SSCTIC STKOV STKUN SYSCON
C161PI Registers, Ordered by Name (continued) Physical Address F0D6H F0D4H FEB4H b FFB0H b FF70H FEB2H b FF6EH b F19CH FEB0H b FF6CH FE12H F0B4H b FFB2H b FF76H F0B2H b FF74H F0B0H b FF72H FE14H FE16H b FF12H 8-Bit Description Addr. E 6BH E 6AH 5AH D8H B8H 59H B7H E CEH 58H B6H 09H E 5AH D9H BBH E 59H BAH E 58H B9H 0AH 0BH 89H E E8H E EAH E 69H RTC High Register RTC Low Register Serial Channel 0 Baud Rate Generator Reload Register Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Reg. (read only) Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Interrupt Control Register Serial Channel 0 Transmit Buffer Reg. (write only) Serial Channel 0 Transmit Interrupt Control Register CPU System Stack Pointer Register SSC Baudrate Register SSC Control Register SSC Error Interrupt Control Register SSC Receive Buffer SSC Receive Interrupt Control Register SSC Transmit Buffer SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register CPU System Configuration Register 2 CPU System Configuration Register 3 RTC Timer 14 Register
1)
Reset Value no no 0000H 0000H 0000H XXXXH 0000H 0000H 0000H 0000H FC00H 0000H 0000H 0000H XXXXH 0000H 0000H 0000H FA00H FC00H 0xx0H 0000H 0000H no
SYSCON2 b F1D0H SYSCON3 b F1D4H T14 F0D2H
Data Sheet
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Table 5 Name T14REL T2 T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T5 T5CON T5IC T6 T6CON T6IC TFR WDT WDTCON XP0IC XP1IC XP2IC XP3IC ZEROS
C161PI Registers, Ordered by Name (continued) Physical Address F0D0H FE40H b FF40H b FF60H FE42H b FF42H b FF62H FE44H b FF44H b FF64H FE46H b FF46H b FF66H FE48H b FF48H b FF68H b FFACH FEAEH FFAEH b F186H b F18EH b F196H b F19EH b FF1CH 8-Bit Description Addr. E 68H 20H A0H B0H 21H A1H B1H 22H A2H B2H 23H A3H B3H 24H A4H B4H D6H 57H D7H E C3H E C7H E CBH E CFH 8EH RTC Timer 14 Reload Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register Trap Flag Register Watchdog Timer Register (read only) Watchdog Timer Control Register IC Data Interrupt Control Register IC Protocol Interrupt Control Register X-Peripheral 2 Interrupt Control Register RTC Interrupt Control Register Constant Value 0's Register (read only)
2)
Reset Value no 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 00xxH 0000H 0000H 0000H 0000H 0000H
1) The system configuration is selected during reset. 2) The reset value depends on the indicated reset source.
Data Sheet
35
1999-07
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Absolute Maximum Ratings Table 6 Parameter Storage temperature Voltage on 9DD pins with respect to ground (9SS) Voltage on any pin with respect to ground (9SS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Power dissipation Absolute Maximum Rating Parameters Symbol Limit Values min. max. 150 6.5 C V V mA mA -65 -0.5 -0.5 -10 Unit Notes
7ST 9DD 9IN
9DD+0.5
10 |100|
3DISS
1.5
W
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (9IN>9DD or 9IN<9SS) the voltage on 9DD pins with respect to ground (9SS) must not exceed the values defined by the absolute maximum ratings.
Data Sheet
36
1999-07
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Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C161PI. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 7 Parameter Standard digital supply voltage Reduced digital supply voltage Digital ground voltage Overload current Absolute sum of overload currents External Load Capacitance Operating Condition Parameters Symbol Limit Values min. max. 5.5 5.5 3.6 3.6 0 5 50 100 V V V V V mA mA pF Active mode, ICPUmax = 25 MHz PowerDown mode Active mode, ICPUmax = 20 MHz PowerDown mode Reference voltage Per pin 2)
3) 3)
Unit Notes
9DD
4.5 2.5 1)
9DD
3.0 2.5 1)
9SS ,OV
|,OV|
&L
Pin drivers in fast edge mode (PDCR.BIPEC = '0') Pin drivers in reduced edge mode (PDCR.BIPEC = '1') 3) SAB-C161PI... SAF-C161PI... SAK-C161PI...
-
50
pF
Ambient temperature
7A
0 -40 -40
70 85 125
C C C
1) Output voltages and output currents will be reduced when 9DD leaves the range defined for active mode. 2) Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. 9OV ! 9DD+0.5V or 9OV 9SS-0.5V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits. 3) Not 100% tested, guaranteed by design characterization.
Data Sheet
37
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Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C161PI and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the C161PI will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C161PI.
DC Characteristics (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Input low voltage XTAL1, P3.0, P3.1, P6.5, P6.6, P6.7 Input low voltage (TTL) Input low voltage (Special Threshold) Input high voltage RSTIN Input high voltage XTAL1, P3.0, P3.1, P6.5, P6.6, P6.7 Input high voltage (TTL) Input high voltage (Special Threshold) Input Hysteresis (Special Threshold) Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (P3.0, P3.1, P6.5, P6.6, P6.7)
Data Sheet
Symbol
Limit Values min. max.
Unit Test Condition - - - - - - - -
9IL1 SR - 0.5 9IL SR - 0.5 9ILS SR - 0.5
0.3 VDD V 0.2 9DD V - 0.1 2.0 V V V V V mV V
9IH1 SR 0.6 9DD 9DD +
0.5
9IH2 SR 0.7 9DD 9DD +
0.5
9IH SR 0.2 9DD 9DD +
+ 0.9 - 0.2 HYS 400 0.5 0.5 - 0.45
9IHS SR 0.8 9DD 9DD +
9OL CC -
,OL = 2.4 mA
9OL2 CC -
0.4
V
,OL2 = 3 mA
38
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DC Characteristics (Standard Supply Voltage Range) (continued) (Operating Conditions apply) Parameter Output low voltage (all other outputs) Output high voltage 1) (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage 1) (all other outputs) Input leakage current (Port 5) Input leakage current (all other) RSTIN inactive current RSTIN active current 2) Read/Write inactive current Read/Write active current ALE inactive current ALE active current 5) Port 6 inactive current Port 6 active current
5) 5) 5) 5) 5) 5) 2)
Symbol
Limit Values min. max. 0.45 -
Unit Test Condition V V V V V nA nA A A A A A A A A A A A pF mA
9OL1 CC - 9OH CC 2.4
,OL = 1.6 mA ,OH = -2.4 mA ,OH = -0.5 mA ,OH = -1.6 mA ,OH = -0.5 mA 0.45V < 9IN < 9DD 0.45V < 9IN < 9DD 9IN = 9IH1 9IN = 9IL 9OUT = 2.4 V 9OUT = 9OLmax 9OUT = 9OLmax 9OUT = 2.4 V 9OUT = 2.4 V 9OUT = 9OL1max 9IN = 9IHmin 9IN = 9ILmax 0 V < 9IN < 9DD I = 1 MHz 7A = 25 C RSTIN = 9IL2 ICPU in [MHz] 7)
RSTIN = 9IH1 ICPU in [MHz] 7) RSTIN = 9IH1 IOSC in [MHz] 7)
0.9 9DD -
9OH1 CC 2.4 ,OZ1 CC ,OZ2 CC ,RSTH 3) ,RSTL 4) ,RWH 3) ,RWL 4) ,ALEL 3) ,ALEH 4) ,P6H 3) ,P6L 4) ,P0H 3) ,P0L 4) ,IL CC &IO CC
- - - -100 - -500 - 500 - -500 - -100 - - - -
8)
- 200 500 -10 - -40 - 40 - -40 - -10 - 20 10 1+ 2*ICPU
0.9 9DD -
PORT0 configuration current XTAL1 input current Pin capacitance 6) (digital inputs/outputs)
Power supply current (5V active) ,DD5 with all peripherals active Idle mode supply current (5V) with all peripherals active Idle mode supply current (5V) with all peripherals deactivated, PLL off, SDD factor = 32
,IDX5 ,IDO5
1+ mA 0.8*ICPU 500 + A 50*IOSC
-
Data Sheet
39
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DC Characteristics (Standard Supply Voltage Range) (continued) (Operating Conditions apply) Parameter Power-down mode supply current (5V) with RTC running Power-down mode supply current (5V) with RTC disabled Symbol Limit Values min. max. 200 + A 25*IOSC 50 A 9DD = 9DDmax IOSC in [MHz] 9DD = 9DDmax
9) 9)
Unit Test Condition
,PDR5 ,PDO5
8)
- -
1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2) These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 K. 3) The maximum current may be drawn while the respective signal line remains inactive. 4) The minimum current must be drawn in order to drive the respective signal line active. 5) This specification is only valid during Reset, or during Hold- or Adapt-mode. During Hold mode Port 6 pins are only affected, if they are used (configured) for CS output and the open drain function is not enabled. 6) Not 100% tested, guaranteed by design characterization. 7) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at 9DDmax and maximum CPU clock with all outputs disconnected and all inputs at 9IL or 9IH. The oscillator also contributes to the total supply current. The given values refer to the worst case, ie. IPDRmax. For lower oscillator frequencies the respective supply current can be reduced accordingly. 8) This parameter is determined mainly by the current consumed by the oscillator. This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. 9) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at 9DD - 0.1 V to 9DD, 9REF = 0 V, all outputs (including pins configured as outputs) disconnected.
Data Sheet
40
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DC Characteristics (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Input low voltage XTAL1, P3.0, P3.1, P6.5, P6.6, P6.7 Input low voltage (TTL) Input low voltage (Special Threshold) Input high voltage RSTIN Input high voltage XTAL1, P3.0, P3.1, P6.5, P6.6, P6.7 Input high voltage (TTL) Input high voltage (Special Threshold) Input Hysteresis (Special Threshold) Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage P3.0, P3.1, P6.5, P6.6, P6.7 Output low voltage (all other outputs) Output high voltage 1) (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage 1) (all other outputs) Input leakage current (Port 5) Input leakage current (all other) RSTIN inactive current
Data Sheet
2)
Symbol
Limit Values min. max.
Unit Test Condition - - - - - - - -
9IL1 SR - 0.5 9IL SR - 0.5 9ILS SR - 0.5
0.3 VDD V 0.8 1.3 V V V V V V mV V
9IH1 SR 0.6 9DD 9DD +
0.5
9IH2 SR 0.7 9DD 9DD +
0.5
9IH SR 1.8
9DD +
0.5
9IHS SR 0.8 9DD 9DD +
- 0.2 HYS 250 0.5 - 0.45
9OL CC -
,OL = 1.6 mA
9OL2 CC - 9OL1 CC -
0.4 0.45
V V V
,OL2 = 1.6 mA ,OL = 1.0 mA ,OH = -0.5 mA
9OH CC 0.9 9DD -
9OH1 CC 0.9 9DD - ,OZ1 CC - ,OZ2 CC - ,RSTH 3) -
41
V nA nA A
,OH = -0.25 mA
0.45V < 9IN < 9DD 0.45V < 9IN < 9DD
200 500 -10
9IN = 9IH1
1999-07
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DC Characteristics (continued) (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter RSTIN active current
2) 5)
Symbol
Limit Values min. max. - -10 - 20 - -10 - -5 - 20 10 -100 - -500 - 500 - -500 - -100 - - - -
Unit Test Condition A A A A A A A A A A pF
Read/Write inactive current Read/Write active current 5) ALE inactive current ALE active current
5) 5) 5)
Port 6 inactive current Port 6 active current
5)
PORT0 configuration current XTAL1 input current Pin capacitance (digital inputs/outputs)
6)
5)
,RSTL ,RWH 3) ,RWL 4) ,ALEL 3) ,ALEH 4) ,P6H 3) ,P6L 4) ,P0H 3) ,P0L 4) ,IL CC &IO CC
4)
Power supply current (3V active) ,DD3 with all peripherals active Idle mode supply current (3V) with all peripherals active
1+ mA 1.1*ICPU 1+ mA 0.5*ICPU 300 + A 30*IOSC 100 + A 10*IOSC 30 A
9IN = 9IL 9OUT = 2.4 V 9OUT = 9OLmax 9OUT = 9OLmax 9OUT = 2.4 V 9OUT = 2.4 V 9OUT = 9OL1max 9IN = 9IHmin 9IN = 9ILmax 0 V < 9IN < 9DD I = 1 MHz 7A = 25 C RSTIN = 9IL2 ICPU in [MHz] 7) ICPU in [MHz] 7) RSTIN = 9IH1 IOSC in [MHz] 7)
9DD = 9DDmax IOSC in [MHz] 9DD = 9DDmax RSTIN = 9IH1
,IDX3
8)
Idle mode supply current (3V) ,IDO3 with all peripherals deactivated, PLL off, SDD factor = 32 Power-down mode supply ,PDR3 current (3V) with RTC running Power-down mode supply ,PDO3 current (3V) with RTC disabled
-
8)
- -
9) 9)
1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2) These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 K. 3) The maximum current may be drawn while the respective signal line remains inactive. 4) The minimum current must be drawn in order to drive the respective signal line active. 5) This specification is only valid during Reset, or during Hold- or Adapt-mode. During Hold mode Port 6 pins are only affected, if they are used (configured) for CS output and the open drain function is not enabled. 6) Not 100% tested, guaranteed by design characterization.
Data Sheet
42
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7) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at 9DDmax and maximum CPU clock with all outputs disconnected and all inputs at 9IL or 9IH. The oscillator also contributes to the total supply current. The given values refer to the worst case, ie. IPDRmax. For lower oscillator frequencies the respective supply current can be reduced accordingly. 8) This parameter is determined mainly by the current consumed by the oscillator. This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. 9) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at 9DD - 0.1 V to 9DD, 9REF = 0 V, all outputs (including pins configured as outputs) disconnected.
1500 1250 1000 750 500 250 4 Figure 9 8 12 16
I [A]
,,'2PD[
,,'2PD[ ,3'5PD[ ,3'5PD[ ,3'2PD[
IOSC [MHz]
Idle and Power Down Supply Current as a Function of Oscillator Frequency
Data Sheet
43
1999-07
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, [mA]
50
IDD5max
IDD5typ
25
IDD3max IDD3typ IID5max IID5typ
IID3max IID3typ
5
5
10
15
20
25
ICPU [MHz]
Figure 10
Supply/Idle Current as a Function of Operating Frequency
Data Sheet
44
1999-07
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AC Characteristics Definition of Internal Timing The internal operation of the C161PI is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see figure below).
3KDVH /RFNHG /RRS 2SHUDWLRQ
I26& I&38
TCL TCL
'LUHFW &ORFN 'ULYH
I26& I&38
TCL TCL
3UHVFDOHU 2SHUDWLRQ
I26& I&38
TCL TCL
Figure 11
Generation Mechanisms for the CPU Clock
The CPU clock signal ICPU can be generated from the oscillator clock signal IOSC via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate ICPU. This influence must be regarded when calculating the timings for the C161PI.
Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4.
The used mechanism to generate the CPU clock is selected during reset via the logic levels on pins P0.15-13 (P0H.7-5). The table below associates the combinations of these three bits with the respective clock generation mode.
Data Sheet
45
1999-07
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Table 8 P0.15-13 (P0H.7-5) 111 110 101 100 011 010 001 000
C161PI Clock Generation Modes CPU Frequency External Clock ICPU = IOSC * F Input Range 1) Notes Default configuration
IOSC * 4 IOSC * 3 IOSC * 2 IOSC * 5 IOSC * 1 IOSC * 1.5 IOSC / 2 IOSC * 2.5
2.5 to 6.25 MHz 3.33 to 8.33 MHz 5 to 12.5 MHz 2 to 5 MHz 1 to 25 MHz 6.66 to 16.6 MHz 2 to 50 MHz 4 to 10 MHz
Direct drive 2) CPU clock via prescaler
1) The external clock input range refers to a CPU clock range of 10...25 MHz. 2) The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation When pins P0.15-13 (P0H.7-5) equal 001B during reset the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of ICPU is half the frequency of IOSC and the high and low time of ICPU (i.e. the duration of an individual TCL) is defined by the period of the input clock IOSC. The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of IOSC for any TCL.
Phase Locked Loop For all combinations of pins P0.15-13 (P0H.7-5) except for 001B and 011B the on-chip phase locked loop is enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. ICPU = IOSC * F). With every F'th transition of IOSC the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of ICPU is constantly adjusted so it is locked to IOSC. The slight variation causes a jitter of ICPU which also effects the duration of individual TCLs.
Data Sheet
46
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The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and figure below). For a period of N * TCL the minimum value is computed using the corresponding deviation DN: (N * TCL)min = N * TCLNOM - DN where N = number of consecutive TCLs DN [ns] = (13.3 + N*6.3) / ICPU [MHz], and 1 N 40.
So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D3 = (13.3 + 3 * 6.3) / 25 = 1.288 ns, and (3TCL)min = 3TCLNOM - 1.288 ns = 58.7 ns (@ ICPU = 25 MHz). This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible.
Note: For all periods longer than 40 TCL the N=40 value can be used (see figure below).
26.5 20
Max.jitter D1 [ns] This approximated formula is valid for 1 1 40 and 10MHz fCPU 25MHz.
10 MHz
16 MHz 20 MHz
10
25 MHz
1 1 5 10 20 40 N
Figure 12
Approximated Maximum Accumulated PLL Jitter
Data Sheet
47
1999-07
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Direct Drive When pins P0.15-13 (P0H.7-5) equal 011B during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of ICPU directly follows the frequency of IOSC so the high and low time of ICPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock IOSC. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: (DC = duty cycle) TCLmin = 1/IOSC * DCmin For two consecutive TCLs the deviation caused by the duty cycle of IOSC is compensated so the duration of 2TCL is always 1/IOSC. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/IOSC.
Note: The address float timings in Multiplexed bus mode (W11 and W45) use the maximum duration of TCL (TCLmax = 1/IOSC * DCmax) instead of TCLmin.
Data Sheet
48
1999-07
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AC Characteristics External Clock Drive XTAL1 (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Direct Drive 1:1 min. Oscillator period WOSC SR High time 2) Low time Rise time
2) 2)
Prescaler 2:1 min. 20 6 6 - - max. - - - 6 6 60 1) 10 10 - -
PLL 1:N min. max. 500 1) - - 10 10
Unit
max. - - - 10 10
40 20 3) 20 - -
3)
ns ns ns ns ns
Fall time 2)
W1 W2 W3 W4
SR SR SR SR
1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation mode. Please see respective table above. 2) The clock input signal must reach the defined levels 9IL and 9IH2. 3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (ICPU) in direct drive mode depends on the duty cycle of the clock input signal.
AC Characteristics External Clock Drive XTAL1 (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Direct Drive 1:1 min. Oscillator period WOSC SR High time 2) Low time 2) Rise time Fall time
2) 2)
Prescaler 2:1 min. 25 8 8 - - max. - - - 6 6 60 1) 10 10 - -
PLL 1:N min. max. 500 1) - - 10 10
Unit
max. - - - 10 10
50 25 3) 25 3) - -
ns ns ns ns ns
W1 W2 W3 W4
SR SR SR SR
1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation mode. Please see respective table above. 2) The clock input signal must reach the defined levels 9IL and 9IH2. 3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (ICPU) in direct drive mode depends on the duty cycle of the clock input signal.
Data Sheet
49
1999-07
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Figure 13
External Clock Drive XTAL1
Note: The main oscillator is optimized for oscillation with a crystal within a frequency range of 4...16 MHz. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is guaranteed by design only (not 100% tested). It is strongly recommended to measure the oscillation allowance (or margin) in the final target system (layout) to determine the optimum parameters for the oscillator operation.
Data Sheet
50
1999-07
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A/D Converter Characteristics (Operating Conditions apply) 4.0V (2.6V) 9AREF 9DD + 0.1V (Note the influence on TUE.) 9SS - 0.1V 9AGND 9SS + 0.2V Parameter Analog input voltage range Basic clock frequency Conversion time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance Symbol Limit Values min. max. Unit Test Condition V MHz
1) 2) 3)
9AIN SR 9AGND IBC 0.5 WC CC -
TUE CC
4)
9AREF
6.25 40 WBC + WS+2WCPU 2 4
- -
5AREF SR - 5ASRC SR - &AIN CC -
WBC / 60
- 0.25
WCPU = 1 / ICPU LSB 9AREF 4.0 V 5) LSB 9AREF 2.6 V k WBC in [ns] 6) 7)
k pF
WS / 450
- 0.25 33
WS in [ns] 7) 8)
7)
1) 9AIN may exceed 9AGND or 9AREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 2) The limit values for IBC must not be exceeded when selecting the CPU frequency and the ADCTC setting. 3) This parameter includes the sample time WS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the basic clock WBC depend on the conversion time programming. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. 4) TUE is tested at 9AREF=5.0V (3.3V), 9AGND=0V, 9DD=4.9V (3.2V). It is guaranteed by design for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see ,OV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be 4 LSB (8 LSB @ 3V). 5) This case is not applicable for the reduced supply voltage range. 6) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within each conversion step. The maximum internal resistance results from the programmed conversion timing. 7) Not 100% tested, guaranteed by design. 8) During the sample time the input capacitance &I can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within WS. After the end of the sample time WS, changes of the analog input voltage have no effect on the conversion result. Values for the sample time WS depend on programming and can be taken from the table below.
Data Sheet
51
1999-07
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Sample time and conversion time of the C161PI's A/D Converter are programmable. The table below should be used to calculate the above timings. The limit values for IBC must not be exceeded when selecting ADCTC. Table 9 A/D Converter Computation Table A/D Converter Basic clock IBC ADCON.13|12 Sample time (ADSTC) WS 00 01 10 11 ADCON.15|14 (ADCTC) 00 01 10 11
ICPU / 4 ICPU / 2 ICPU / 16 ICPU / 8
WBC * 8 WBC * 16 WBC * 32 WBC * 64
Converter Timing Example: Assumptions: Basic clock Sample time Conversion time
ICPU IBC WS WC
= 25 MHz (i.e. WCPU = 40 ns), ADCTC = '00', ADSTC = '00'. = ICPU / 4 = 6.25 MHz, i.e. WBC = 160 ns. = WBC * 8 = 1280 ns. = WS + 40 WBC + 2 WCPU = (1280 + 6400 + 80) ns = 7.8 s.
Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Table 10 Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Memory Cycle Variables Symbol Values TCL * 2TCL * (15 - ) 2TCL * (1 - )
WA WC WF
52
Data Sheet
1999-07
&3,
Testing Waveforms
2.4 V
1.8 V Test Points
1.8 V
0.45 V
0.8 V
0.8 V
AC inputs during testing are driven at 2.4 V for a logic `1' and 0.45 V for a logic `0'. Timing measurements are made at 9IH min for a logic '1' and 9IL max for a logic '0'.
Figure 14
Input Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded 9OH/9OL level occurs (,OH/,OL = 20 mA).
Figure 15
Float Waveforms
Data Sheet
53
1999-07
&3,
AC Characteristics Multiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD max. - - - - - 6 26 - - 20 + WC 40 + WC 40 + WA + WC min. TCL - 10 + WA TCL - 16 + WA TCL - 10 + WA TCL - 10 + WA -10 + WA - - 2TCL - 10 + WC 3TCL10+WC - - - - - - - - 6 TCL + 6 - - 2TCL - 20 + WC 3TCL - 20 + WC 3TCL - 20 + W A + WC 4TCL - 30 + 2WA + WC - 2TCL - 14 + WF max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
W5 W6 W7 W8 W9
CC 10 + WA CC 4 + WA CC 10 + WA CC 10 + WA CC -10 + WA
W10 CC - W11 CC - W12 CC 30 + WC W13 CC 50 + WC W14 SR - W15 SR - W16 SR - W17 SR - W18 SR 0 W19 SR -
50 + 2WA - + WC - 26 + WF 0 -
Data Sheet
54
1999-07
&3,
Multiplexed Bus (Standard Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. Data valid to WR Data hold after WR max. - - - - 10 - WA 40 + WC + 2WA - - - 0 20 16 + WC 36 + WC - - min. 2TCL - 20 + WC 2TCL - 14 + WF 2TCL - 14 + WF 2TCL - 14 + WF -4 - WA - - - - - 10 - WA 3TCL - 20 + WC + 2WA - - - 0 TCL 2TCL - 24 + WC 3TCL - 24 + WC - - max. ns ns ns ns ns ns
W22 CC 20 + WC W23 CC 26 + WF
ALE rising edge after RD, W25 CC 26 + WF WR Address hold after RD, WR ALE falling edge to CS 1) CS low to Valid Data In
1)
W27 CC 26 + WF W38 CC -4 - WA W39 SR - W40 CC 46 + WF W42 CC 16 + WA W43 CC -4 + WA
CS hold after RD, WR 1) ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay)
3TCL - 14 +WF TCL - 4 + WA -4 + WA - - - - 2TCL - 10 + WC 3TCL - 10 + WC
ns ns ns ns ns ns ns ns ns
Address float after RdCS, W44 CC - WrCS (with RW delay) Address float after RdCS, W45 CC - WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay)
W46 SR - W47 SR - W48 CC 30 + WC W49 CC 50 + WC
Data Sheet
55
1999-07
&3,
Multiplexed Bus (Standard Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS max. - - 20 + WF - - min. 2TCL - 14 + WC 0 - 2TCL - 20 + WF 2TCL - 20 + WF - - 2TCL - 20 + WF - - max. ns ns ns ns ns
W50 CC 26 + WC W51 SR 0 W52 SR - W54 CC 20 + WF W56 CC 20 + WF
1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below).
Data Sheet
56
1999-07
&3,
AC Characteristics Multiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD max. - - - - - 6 31 - - 22 + WC 47 + WC 49 + WA + WC min. TCL - 14 + WA TCL - 20 + WA TCL - 10 + WA TCL - 10 + WA -10 + WA - - 2TCL - 16 + WC 3TCL - 16 + WC - - - - - - - - 6 TCL + 6 - - 2TCL - 28 + WC 3TCL - 28 + WC 3TCL - 30 + W A + WC 4TCL - 43 + 2WA + WC - 2TCL - 14 + WF max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
W5 W6 W7 W8 W9
CC 11 + WA CC 5 + WA CC 15 + WA CC 15 + WA CC -10 + WA
W10 CC - W11 CC - W12 CC 34 + WC W13 CC 59 + WC W14 SR - W15 SR - W16 SR - W17 SR - W18 SR 0 W19 SR -
57 + 2WA - + WC - 36 + WF 0 -
Data Sheet
57
1999-07
&3,
Multiplexed Bus (Reduced Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. Data valid to WR Data hold after WR max. - - - - 10 - WA min. 2TCL - 26 + WC 2TCL - 14 + WF 2TCL - 14 + WF 2TCL - 14 + WF -8 - WA - - - - 10 - WA 3TCL - 28 + WC + 2WA - - - 0 TCL 2TCL - 30 + WC 3TCL - 30 + WC - - - max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
W22 CC 24 + WC W23 CC 36 + WF
ALE rising edge after RD, W25 CC 36 + WF WR Address hold after RD, WR ALE falling edge to CS 1) CS low to Valid Data In
1)
W27 CC 36 + WF W38 CC -8 - WA W39 SR - W40 CC 57 + WF W42 CC 19 + WA W43 CC -6 + WA
47 - + WC+ 2WA - - - 0 25 20 + WC 45 + WC - - - 3TCL - 18 + WF TCL - 6 + WA -6 + WA - - - - 2TCL - 12 + WC 3TCL - 12 + WC 2TCL - 22 + WC
CS hold after RD, WR 1) ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay)
Address float after RdCS, W44 CC - WrCS (with RW delay) Address float after RdCS, W45 CC - WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS
W46 SR - W47 SR - W48 CC 38 + WC W49 CC 63 + WC W50 CC 28 + WC
Data Sheet
58
1999-07
&3,
Multiplexed Bus (Reduced Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS max. - 30 + WF - - 0 - 2TCL - 20 + WF 2TCL - 20 + WF min. - 2TCL - 20 + WF - - max. ns ns ns ns
W51 SR 0 W52 SR - W54 CC 30 + WF W56 CC 30 + WF
1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below).
Data Sheet
59
1999-07
&3,
W5
ALE
W16
W25
W38
CSxL A22-A16 (A15-A8) BHE, CSxE 5HDG &\FOH BUS Address
W39
W40
W17
Address
W27 W54 W19 W18
Data In
W6
W7
W8
RD
W10 W14 W44 W12 W46 W48 W51 W52
W42
RdCSx
:ULWH &\FOH BUS Address Data Out
W23 W10 W12 W50 W48 W56
W8
WR, WRL, WRH WrCSx
W22
W42
W44
Figure 16
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE
Data Sheet
60
1999-07
&3,
W5
ALE
W16
W25
W38 W39
CSxL
W40
A22-A16 (A15-A8) BHE, CSxE 5HDG &\FOH BUS
W17
Address
W27 W54 W19 W18
W6
W7
Address
Data In
W8
RD
W10 W14 W44 W12 W46 W48 W51 W52
W42
RdCSx
:ULWH &\FOH BUS Address Data Out
W23 W10 W12 W50 W48 W56
W8
WR, WRL, WRH WrCSx
W22
W42
W44
Figure 17
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE
61 1999-07
Data Sheet
&3,
W5
ALE
W16
W25
W38
CSxL
W39
W40
A22-A16 (A15-A8) BHE, CSxE 5HDG &\FOH BUS
W17
Address
W27 W54 W19 W18
W6
W7
Address
Data In
W9
RD
W11
W15 W13 W51 W52
W43
RdCSx
W45
W47 W49
:ULWH &\FOH BUS Address Data Out
W23 W9 W56
W11
W22 W13 W50 W49
WR, WRL, WRH WrCSx
W43
W45
Figure 18
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE
62 1999-07
Data Sheet
&3,
W5
ALE
W16 W38 W39
W25
W40
CSxL
A22-A16 (A15-A8) BHE, CSxE 5HDG &\FOH BUS
W17
Address
W27 W54 W19 W18
W6
W7
Address
Data In
W9
RD
W11
W15 W13 W51 W52
W43
RdCSx
W45
W47 W49
:ULWH &\FOH BUS Address Data Out
W23 W56
W9
WR, WRL, WRH WrCSx
W11 W13
W22
W43
W45 W49
W50
Figure 19
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE
63 1999-07
Data Sheet
&3,
AC Characteristics Demultiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay 1)) Data float after RD rising edge (no RW-delay 1)) Data valid to WR max. - - - - - - 20 + WC 40 + WC 40 + min. TCL - 10 + WA TCL - 16 + WA TCL - 10 + WA -10 + WA 2TCL - 10 + WC 3TCL - 10 + WC - - - - 0 - - - - - - - 2TCL - 20 + WC 3TCL - 20 + WC 3TCL - 20 + W A + WC 4TCL - 30 + 2WA + WC - 2TCL - 14 + 22WA + WF 1) TCL - 10 + 22WA + WF 1) - max. ns ns ns ns ns ns ns ns ns ns ns ns
W5 W6 W8 W9
CC 10 + WA CC 4 + WA CC 10 + WA CC -10 + WA
W12 CC 30 + WC W13 CC 50 + WC W14 SR - W15 SR - W16 SR - W17 SR - W18 SR 0 W20 SR - W21 SR - W22 CC 20 + WC
WA + WC
50 + 2WA + WC - 26 + 2WA + WF
1)
10 + - 1) 2WA + WF - 2TCL - 20 + WC
ns
ns
Data Sheet
64
1999-07
&3,
Demultiplexed Bus (Standard Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. Data hold after WR max. - - - 10 - WA 40 + WC + 2WA - - min. TCL - 10 + WF -10 + WF 0 + WF -4 - WA - TCL - 14 + WF TCL - 4 + WA -4 + WA - - 2TCL - 10 + WC 3TCL - 10 + WC 2TCL - 14 + WC 0 - - - - - 10 - WA 3TCL - 20 + WC + 2WA - - max. ns ns ns ns ns ns ns
W24 CC 10 + WF
ALE rising edge after RD, W26 CC -10 + WF WR Address hold after WR 2) ALE falling edge to CS
3)
CS low to Valid Data In 3) CS hold after RD, WR 3) ALE falling edge to RdCS, WrCS (with RWdelay) ALE falling edge to RdCS, WrCS (no RWdelay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay) 1) Data float after RdCS (no RW-delay) 1)
Data Sheet
W28 CC 0 + WF W38 CC -4 - WA W39 SR - W41 CC 6 + WF W42 CC 16 + WA W43 CC -4 + WA W46 SR - W47 SR - W48 CC 30 + WC W49 CC 50 + WC W50 CC 26 + WC W51 SR 0 W53 SR - W68 SR -
-
-
ns
16 + WC 36 + WC - - - - 20 + WF 0 + WF
2TCL - 24 + WC
ns
3TCL - 24 ns + WC - - - - ns ns ns ns
2TCL - 20 ns + 2WA + WF 1) TCL - 20 ns 1) + 2WA + WF
1999-07
65
&3,
Demultiplexed Bus (Standard Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. Address hold after RdCS, WrCS Data hold after WrCS max. - - min. -6 + WF - max. ns ns
W55 CC -6 + WF W57 CC 6 + WF
WF
TCL - 14 + -
1) RW-delay and WA refer to the next following bus cycle (including an access to an on-chip X-Peripheral). 2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. 3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below).
Data Sheet
66
1999-07
&3,
AC Characteristics Demultiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay 1)) Data float after RD rising edge (no RW-delay 1)) Data valid to WR max. - - - - - - 22 + WC 47 + WC 49 + min. TCL - 14 + WA TCL - 20 + WA TCL - 10 + WA -10 + WA 2TCL - 16 + WC 3TCL - 16 + WC - - - - 0 - - - - - - - 2TCL - 28 + WC 3TCL - 28 + WC 3TCL - 30 + W A + WC 4TCL - 43 + 2WA + WC - 2TCL - 14 + 2WA + WF max. ns ns ns ns ns ns ns ns ns ns ns ns
W5 W6 W8 W9
CC 11 + WA CC 5 + WA CC 15 + WA CC -10 + WA
W12 CC 34 + WC W13 CC 59 + WC W14 SR - W15 SR - W16 SR - W17 SR - W18 SR 0 W20 SR - W21 SR - W22 CC 24 + WC
W A + WC
57 + 2WA + WC - 36 + 2WA + WF
1)
1)
15 + - 1) 2WA + WF - 2TCL - 26 + WC
TCL - 10 + 2WA + WF 1) -
ns
ns
Data Sheet
67
1999-07
&3,
Demultiplexed Bus (Reduced Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. Data hold after WR max. - - - 10 - WA 47 + WC + 2WA - - min. TCL - 10 + WF -12 + WF 0 + WF -8 - WA - TCL - 16 + WF TCL - 6 + WA -6 + WA - - 2TCL - 12 + WC 3TCL - 12 + WC 2TCL - 22 + WC 0 - - - - - 10 - WA 3TCL - 28 + WC + 2WA - - max. ns ns ns ns ns ns ns
W24 CC 15 + WF
ALE rising edge after RD, W26 CC -12 + WF WR Address hold after WR 2) ALE falling edge to CS
3)
CS low to Valid Data In 3) CS hold after RD, WR 3) ALE falling edge to RdCS, WrCS (with RWdelay) ALE falling edge to RdCS, WrCS (no RWdelay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay) 1) Data float after RdCS (no RW-delay) 1)
Data Sheet
W28 CC 0 + WF W38 CC -8 - WA W39 SR - W41 CC 9 + WF W42 CC 19 + WA W43 CC -6 + WA W46 SR - W47 SR - W48 CC 38 + WC W49 CC 63 + WC W50 CC 28 + WC W51 SR 0 W53 SR - W68 SR -
-
-
ns
20 + WC 45 + WC - - - - 30 + WF 5 + WF
2TCL - 30 + WC
ns
3TCL - 30 ns + WC - - - - ns ns ns ns
2TCL - 20 ns + 2WA + WF 1) TCL - 20 ns 1) + 2WA + WF
1999-07
68
&3,
Demultiplexed Bus (Reduced Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. Address hold after RdCS, WrCS Data hold after WrCS max. - - min. -16 + WF TCL - 16 + WF - - max. ns ns
W55 CC -16 + WF W57 CC 9 + WF
1) RW-delay and WA refer to the next following bus cycle (including an access to an on-chip X-Peripheral). 2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. 3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below).
Data Sheet
69
1999-07
&3,
W5
ALE
W16
W26
W38
CSxL
W39
W41
A22-A16 A15-A0 BHE, CSxE 5HDG &\FOH BUS (D15-D8) D7-D0
W17
Address
W28 W55 W20 W18
Data In
W6
W8
RD
W14 W12 W51
W42
RdCSx
W46 W48
W53
:ULWH &\FOH BUS (D15-D8) D7-D0 WR, WRL, WRH
W24
Data Out
W8 W12 W42
W22
W57
W50 W48
WrCSx
Figure 20
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE
70 1999-07
Data Sheet
&3,
W5
ALE
W16 W38 W39
W26
W41
CSxL
A22-A16 A15-A0 BHE, CSxE 5HDG &\FOH BUS (D15-D8) D7-D0
W17
Address
W28 W55 W20 W18
Data In
W6
W8
RD
W14 W12 W51 W53
W42
RdCSx
W46 W48
:ULWH &\FOH BUS (D15-D8) D7-D0 WR, WRL, WRH
W24
Data Out
W8 W12 W42
W22
W57
W50 W48
WrCSx
Figure 21
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE
71 1999-07
Data Sheet
&3,
W5
ALE
W16
W26
W38
CSxL
W39
W41
A22-A16 A15-A0 BHE, CSxE 5HDG &\FOH BUS (D15-D8) D7-D0 RD
W17
Address
W28 W55 W21 W18
Data In
W6
W9 W15 W43 W13 W47 W49 W51 W68
RdCSx
:ULWH &\FOH BUS (D15-D8) D7-D0 WR, WRL,WRH
W24
Data Out
W9
W22 W13 W50 W49
W57
W43
WrCSx
Figure 22
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE
72 1999-07
Data Sheet
&3,
W5
ALE
W16 W38 W39
W26
W41
CSxL
A22-A16 A15-A0 BHE,CSxE 5HDG &\FOH BUS (D15-D8) D7-D0
W17
Address
W28 W55 W21 W18
Data In
W6
W9
RD
W15 W13 W51 W68
W43
RdCSx
W47 W49
:ULWH &\FOH BUS (D15-D8) D7-D0
W24
Data Out
W9
WR, WRL, WRH
W22 W13
W57
W43
WrCSx
W50 W49
Figure 23
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE
73 1999-07
Data Sheet
&3,
AC Characteristics CLKOUT and READY (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) max. 40 - - 4 4 10 + WA - - - - - min. 2TCL TCL - 6 TCL - 10 - - 0 + WA 14 4 - - 4 4 10 + WA - - max. 2TCL ns ns ns ns ns ns ns ns ns ns ns ns
W29 W30 W31 W32 W33 W34
CC 40 CC 14 CC 10 CC - CC - CC 0 + WA
W35 SR 14 W36 SR 4 W37 SR 54 W58 SR 14 W59 SR 4
SR 0
2TCL + W58 - 14 4 - - TCL - 20 + 2WA + WC + WF 2)
Async. READY hold time W60 after RD, WR high (Demultiplexed Bus) 2)
0 0 + 2WA + WC + WF 2)
1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2WA and WC refer to the next following bus cycle, WF refers to the current bus cycle. The maximum limit for W60 must be fulfilled if the next following bus cycle is READY controlled.
Data Sheet
74
1999-07
&3,
AC Characteristics CLKOUT and READY (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) max. 40 - - 12 8 8 + WA - - - - - min. 2TCL TCL - 10 TCL - 12 - - 0 + WA 18 4 - - 12 8 8 + WA - - max. 2TCL ns ns ns ns ns ns ns ns ns ns ns ns
W29 W30 W31 W32 W33 W34
CC 40 CC 15 CC 13 CC - CC - CC 0 + WA
W35 SR 18 W36 SR 4 W37 SR 68 W58 SR 18 W59 SR 4
SR 0
2TCL + W58 - 18 4 - - TCL - 25 + 2WA + WC + WF 2)
Async. READY hold time W60 after RD, WR high (Demultiplexed Bus) 2)
0 0 + 2WA + WC + WF 2)
1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2WA and WC refer to the next following bus cycle, WF refers to the current bus cycle. The maximum limit for W60 must be fulfilled if the next following bus cycle is READY controlled.
Data Sheet
75
1999-07
&3,
Running cycle 1)
READY waitstate
MUX/Tristate 6)
CLKOUT
W32 W30 W34
W33 W31 W29
7)
ALE
Command RD, WR Sync READY
2)
W35
3)
W36
W35
3)
W36
W58
Async READY
3)
W59
W58
3)
W59 W37
W60
4)
5)
see 6)
Figure 24
CLKOUT and READY
Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command depends on RW-delay. 3) READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4) READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 5) If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill W37 in order to be safely synchronized. This is guaranteed, if READY is removed in reponse to the command (see Note 4)). 6) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7) The next external bus cycle may start here.
Data Sheet
76
1999-07
&3,
Package Outlines
Plastic Package, P-MQFP-100-2 (SMD) (Plastic Metric Quad Flat Package)
Figure 25
Data Sheet
77
1999-07
C161PI
Package Outlines (continued)
Plastic Package, P-TQFP-100-1 (SMD) (Plastic Thin Metric Quad Flat Package)
Figure 26
Sorts of Packing Package outlines for tubes, trays, etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Dimensions in mm
Data Sheet
78
1999-07
&3,
Data Sheet
79
1999-07
&3,
Published by Infineon Technologies AG Data Sheet 80 1999-07

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